# Hardware design interview questions

Following are Hardware design interview questions: Reply if you have any answers.

1. Give two ways of converting a two input NAND gate to an inverter

2. Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt)

3. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?

4. Give a circuit to divide frequency of clock cycle by two

5. Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)

6. Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors)

7. The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this?

8. What are the different Adder circuits you studied?

9. Give the truth table for a Half Adder. Give a gate level implementation of the same.

10. Draw a Transmission Gate-based D-Latch.

11. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output)

12. How do you detect if two 8-bit signals are same?

13. How do you detect a sequence of “1101” arriving serially from a signal line?

14. Design any FSM in VHDL or Verilog.

15. Explain RC circuit.s charging and discharging.

16. Explain the working of a binary counter.

17. Describe how you would reverse a singly linked list.

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1. Give two ways of converting a two input NAND gate to an inverter

2. Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt)

3. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?

4. Give a circuit to divide frequency of clock cycle by two

5. Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)

6. Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors)

7. The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this?

8. What are the different Adder circuits you studied?

9. Give the truth table for a Half Adder. Give a gate level implementation of the same.

10. Draw a Transmission Gate-based D-Latch.

11. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output)

12. How do you detect if two 8-bit signals are same?

13. How do you detect a sequence of “1101″ arriving serially from a signal line?

14. Design any FSM in VHDL or Verilog.

15. Explain RC circuit.s charging and discharging.

16. Explain the working of a binary counter.

17. Describe how you would reverse a singly linked list.

please send me the answers…

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Dear sir\Madam,

I am vikas pandey.I have got your mail id from net. I have done diploma in computer engineering & looking for a job. I am hereby sending my cv to you. please do consider me if you have any suitable opening for me.

Thanking you.

Vikas pandey