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- Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
- Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram.
- In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
- Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
- Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
- For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
Draw a 6-T SRAM Cell and explain the Read and Write operations
- Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
- What happens if we use an Inverter instead of the Differential Sense Amplifier?
- Draw the SRAM Write Circuitry
- Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
- What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
- How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s performance?
- What’s the critical path in a SRAM?
- Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
- Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
- In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
- How can you model a SRAM at RTL Level?
- What’s the difference between Testing & Verification?
- For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
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